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1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead pdip 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead soic 1 2 3 4 8 7 6 5 cs so wp gnd vcc hol d sck si 8-lead tssop 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd 8-lead ultra thin sap vcc hold sck s i cs so wp gnd 1 2 3 4 8 7 6 5 8-ball dbga2 bottom view bottom view features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? data sheet describes mode 0 operation ? low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 5.5v) ? 20 mhz clock rate (5v) ? 64-byte page mode and byte write operation ? block write protection ? protect 1/4, 1/2, or entire array ? write protect ( wp) pin and write disable instructions for both hardware and software data protection ? self-timed write cycle (5 ms max) ? high-reliability ? endurance: 1 million write cycles ? data retention: >100 years ? 8-lead pdip, 8-lead eiaj soic, 8-lead jedec soic, 8-lead tssop, 8-ball dbga2 and 8- lead ultra thin sap packages ? lead-free/halogen-free ? available in automotive ? die sales: wafer form, waffle pack, and bumped die description the at25128a/256a provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read only memory (eeprom) organized as 16,384/32,768 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the devices are available in space saving 8-lead pdip, 8-lead eiaj soic, 8-lead jedec soic, 8-lead tssop, 8-ball dbga2 and 8-lead sap packages. in addition, the entire family is available in 2.7v (2.7v to 5.5v) and 1.8v (1.8v to 5.5v) versions. the at25128a/256a is enabled through the chip select pin ( cs) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no sepa- rate erase cycle is required before write. 3368j?seepr?06/07 spi serial eeproms 128k (16,384 x 8) 256k (32,768 x 8) at25128a at25256a not recommended for new design
2 3368j?seepr?06/07 at25128a_256a block write protection is enabled by programming the status register with top ?, top ? or entire array of write protection. separate program enable and program disable instructions are pro- vided for additional data protection. hardware data protection is provided via the w p pin to protect against inadvertent write attempts to the status register. the h o l d pin may be used to suspend any serial communication without resetting the serial sequence. table 0-1. pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input nc no connect 1. absolute maximum ratings* operating temperature ???????????????????????????????????? ? 55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ???????????????????????????????????????? ? 65 ? c to +150 ? c voltage on any pin with respect to ground ???????????????????????????????????????? ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 3368j?seepr?06/07 at25128a_256a figure 1-1. block diagram note: 1. this parameter is characterized and is not 100% tested. 16384/32768 x 8 table 1-1. pin capacitance (1) applicable over recommended operating range from t a =25 ? c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out =0v c in input capacitance ( cs, sck, si, wp, hold) 6 pf v in =0v
4 3368j?seepr?06/07 at25128a_256a note: 1. v il min and v ih max are reference only and are not tested. table 1-2. dc characteristics applicable over recommended operating range from t ai = ? 40c to +85c, v cc = +1.8v to +5.5v, t ae = ? 40 ? c to +125 ? c, v cc = +1.8v to +5.5v(unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v at 20 mhz, so = open, read 9.0 10.0 ma i cc2 supply current v cc = 5.0v at 10 mhz, so = open, read, write 5.0 7.0 ma i cc3 supply current v cc = 5.0v at 1 mhz, so = open, read, write 2.2 3.5 ma i sb1 standby current v cc = 1.8v, cs = v cc 0.2 3.0 a i sb2 standby current v cc = 2.7v, cs = v cc 0.5 3.0 a i sb3 standby current v cc = 5.0v, cs = v cc 2.0 5.0 a i il input leakage v in =0vtov cc ? 3.0 3.0 a i ol output leakage v in =0vtov cc ,t ac =0 ? cto70 ? c ? 3.0 3.0 a v il (1) input low-voltage ? 1.0 v cc x 0.3 v v ih (1) input high-voltage v cc x 0.7 v cc + 0.5 v v ol1 output low-voltage 3.6 ? v cc ? 5.5v i ol = 3.0 ma 0.4 v v oh1 output high-voltage i oh = ? 1.6 ma v cc ? 0.8 v v ol2 output low-voltage 1.8v ? v cc ? 3.6v i ol = 0.15 ma 0.2 v v oh2 output high-voltage i oh = ? 100 a v cc ? 0.2 v
5 3368j?seepr?06/07 at25128a_256a table 1-3. ac characteristics applicable over recommended operating range from t ai = ? 40 ? cto+85 ? c, t ae = ? 40 ? c to +125 ? c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units f sck sck clock frequency 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 0 0 0 20 10 5 mhz t ri input rise time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 2 2 2 s t fi input fall time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 2 2 2 s t wh sck high time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 20 40 80 ns t wl sck low time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 20 40 80 ns t cs cs high time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 100 100 200 ns t css cs setup time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 100 100 200 ns t csh cs hold time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 100 100 200 ns t su data in setup time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 5 10 20 ns t h data in hold time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 5 10 20 ns t hd hold setup time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 5 10 20 ns t cd hold hold time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 5 10 20 ns t v output valid 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 0 0 0 20 40 80 ns t ho output hold time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 0 0 0 ns t lz hold to output low z 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 0 0 0 25 50 100 ns
6 3368j?seepr?06/07 at25128a_256a notes: 1. this parameter is characterized and is not 100% tested. contact atmel for further information. t hz hold to output high z 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 25 50 100 ns t dis output disable time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 25 50 100 ns t wc write cycle time 4.5 ? 5.5 2.7 ? 5.5 1.8 ? 5.5 5 5 5 ms endurance (1) 5.0v, 25 ? c, page mode 1m write cycles table 1-3. ac characteristics (continued) applicable over recommended operating range from t ai = ? 40 ? cto+85 ? c, t ae = ? 40 ? c to +125 ? c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units
7 3368j?seepr?06/07 at25128a_256a 2. serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25128a/256a always operates as a slave. transmitter/receiver: the at25128a/256a has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with c s going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25128a/256a, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the at25128a/256a is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the h o l d pin is used in conjunction with the c s pin to select the at25128a/256a. when the device is selected and a serial sequence is underway, h o l d can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communi- cation, the h o l d pin is brought high while the sck pin is low (sck may still toggle during hold). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin ( wp) will allow normal read/write operations when held high. when the wp pin is brought low and wpen bit is ?1?, all write operations to the status reg- ister are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow the user to install the at25128a/256a in a system with the wp pin tied to ground and still be able to write to the status register. all w p pin functions are enabled when the wpen bit is set to ?1?.
8 3368j?seepr?06/07 at25128a_256a figure 2-1. spi serial interface at25128a/256a
9 3368j?seepr?06/07 at25128a_256a 3. functional description the at25128a/256a is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the at25128a/256a utilizes an 8-bit instruction register. the list of instructions and their opera- tion codes are contained in see table 4-3 . all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. write enable (wren): the device will power-up in the write disable state when v cc is applied. all programming instructions must therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is independent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. table 3-1. instruction set for the at25128a/256a instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array table 3-2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rd y table 3-3. read status register bit definition bit definition bit0( rd y) bit 0 = ?0? ( rd y) indicates the device is ready. bit 0 = ?1? indicates the write cycle is in progress. bit 1 (wen) bit1=0 indicates the device is not write enabled. bit 1 = ?1? indicates the device is write enabled. bit 2 (bp0) see table 3-4 on page 10 . bit 3 (bp1) see table 3-4 on page 10 . bits 4 ? 6 are 0s when device is not in an internal write cycle. bit 7 (wpen) see table 3-5 on page 10 . bits 0 ? 7 are ?1?s during an internal write cycle.
10 3368j?seepr?06/07 at25128a_256a write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection. the at25128a/256a is divided into four array segments. top quarter (1/4), top half (1/2), or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protection levels and correspond- ing status register control bits are shown in table 3-4 . the three bits, bp0, bp1, and wpen are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. wren, t wc , rdsr). the wrsr instruction also allows the user to enable or disable the write protect ( w p) pin through the use of the write protect enable (wpen) bit. hardware write protection is enabled when the w p pin is low and the wpen bit is ?1?. hardware write protection is disabled when either the w p pin is high or the wpen bit is ?0?. when the device is hardware write protected, writes to the status register, including the block protect bits and the wpen bit, and the block- protected sections in the memory array are disabled. writes are only allowed to sections of the memory which are not block-protected. note: when the wpen bit is hardware write protected, it cannot be changed back to ?0?, as long as the wp pin is held low. read sequence (read): reading the at25128a/256a via the so pin requires the follow- ing sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (see table 3-6 on page 11 ). upon com- pletion, any data on the si line will be ignored. the data (d7 - d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be continued since the byte address is auto- matically incremented and data will continue to be shifted out. when the highest address is table 3-4. block write protect bits level status register bits array addresses protected bp1 bp0 at25128a at25256a 0 0 0 none none 1(1/4) 0 1 3000 ? 3fff 6000 ? 7fff 2(1/2) 1 0 2000 ? 3fff 4000 ? 7fff 3(all) 1 1 0000 ? 3fff 0000 ? 7fff table 3-5. wpen operation wpen wp wen protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
11 3368j?seepr?06/07 at25128a_256a reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. write sequence (write): in order to program the at25128a/256a, two separate instruc- tions must be executed. first, the device must be write enabled via the write enable (wren) instruction. then a write instruction may be executed. also, the address of the memory loca- tion(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the c s line is pulled low to select the device, the write op-code is transmitted via the si line followed by the byte address and the data (d7 - d0) to be programmed (see table 3-6 ). programming will start after the cs pin is brought high. (the low-to-high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read status register (rdsr) instruction. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0, the write cycle has ended. only the read status register instruction is enabled during the write programming cycle. the at25128a/256a is capable of a 64-byte page write operation. after each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant. if more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. the at25128a/256a is automatically returned to the write disable state at the completion of a write cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to re-initiate the serial communication. table 3-6. address key address at25128a at25256a a n a 13 ? a 0 a 14 ? a 0 don?t care bits a 15 ? a 14 a 15
12 3368j?seepr?06/07 at25128a_256a 4. timing diagrams (for spi mode 0 (0, 0)) figure 4-1. synchronous data timing figure 4-2. wren timing so v oh v ol hi-z hi-z t v valid in si v ih v il t h t su t dis sck v ih v il t wh t csh cs v ih v il t css t cs t wl t ho
13 3368j?seepr?06/07 at25128a_256a figure 4-3. wrdi timing figure 4-4. rdsr timing figure 4-5. wrsr timing cs sck 01234567891011121314 si instruction so 76543210 data out msb high impedance 15
14 3368j?seepr?06/07 at25128a_256a figure 4-6. read timing figure 4-7. write timing figure 4-8. hold timing so sck hold t cd t hd t hz t lz t cd t hd cs
15 3368j?seepr?06/07 at25128a_256a notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?u? designates green package + rohs compliant. 3. available in waffle pack and wafer form; order as sl788 for wafer form. bumped die available upon request. please contact serial interface marketing. 5. at25128a ordering information (1) ordering code package operation range at25128a-10pu-2.7 (2) at25128a-10pu-1.8 (2) at25128an-10su-2.7 (2) at25128an-10su-1.8 (2) at25128aw-10su-2.7 (2) at25128aw-10su-1.8 (2) at25128a-10tu-2.7 (2) at25128a-10tu-1.8 (2) at25128au2-10uu-1.8 (2) at25128ay7-10yh-1.8 (2) 8p3 8p3 8s1 8s1 8s2 8s2 8a2 8a2 8u2-1 8y7 lead-free/halogen-free/ industrial temperature ( ? 40 ? cto85 ? c) at25128a-w1.8-11 (3) die sale industrial temperature ( ? 40 ? cto85 ? c) package type 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8u2-1 8-ball, die ball grid array package (dbga2) 8a2 8-lead, 4.4 mm body, thin shrink small outline package (tssop) 8y7 8-lead, 6.00 mm x 4.90 mm body, ultra thin, dual footprint, non-leaded, small array package (sap) options ? 2.7 low-voltage (2.7v to 5.5v) ? 1.8 low-voltage (1.8v to 5.5v)
16 3368j?seepr?06/07 at25128a_256a notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?u? designates green package + rohs compliant. 3. available in waffle pack and wafer form; order as sl788 for wafer form. bumped die available upon request. please contact serial interface marketing. at25256a ordering information (1) ordering code package operation range at25256a-10pu-2.7 (2) at25256a-10pu-1.8 (2) at25256an-10su-2.7 (2) at25256an-10su-1.8 (2) at25256aw-10su-2.7 (2) at25256aw-10su-1.8 (2) at25256a-10tu-2.7 (2) at25256a-10tu-1.8 (2) at25256au2-10uu-1.8 (2) at25256ay7-10yh-1.8 (2) 8p3 8p3 8s1 8s1 8s2 8s2 8a2 8a2 8u2-1 8y7 lead-free/halogen-free/ industrial temperature ( ? 40 ? cto85 ? c) at25256a-w1.8-11 (3) die sale industrial temperature ( ? 40 ? cto85 ? c) package type 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8u2-1 8-ball, die ball grid array package (dbga2) 8a2 8-lead, 4.4 mm body, thin shrink small outline package (tssop) 8y7 8-lead, 6.00 mm x 4.90 mm body, ultra thin, dual footprint, non-leaded, small array package (sap) options ? 2.7 low-voltage (2.7v to 5.5v) ? 1.8 low-voltage (1.8v to 5.5v)
17 3368j?seepr?06/07 at25128a_256a 6. packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba, for additional information . 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a ? ? 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 ? ? 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
18 3368j?seepr?06/07 at25128a_256a 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 3/17/05 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 c common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0? ? 8? ? ? e e 1 1 n n top view top view c c e1 e1 end view a a b b l l a1 a1 e e d d side view side view
19 3368j?seepr?06/07 at25128a_256a 8s2 ? eiaj soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 10/7/03 8s2 c common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b and c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 ? 0 8 e 1.27 bsc 4 end view side view e b a a1 d e n 1 c e1 ? l top view
20 3368j?seepr?06/07 at25128a_256a 8u2-1 ? dbga2 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. po8u2-1 a 6/24/03 common dimensions (unit of measure = mm) symbol min nom max note 8u2-1, 8-ball, 2.35 x 3.73 mm body, 0.75 mm pitch, small die ball grid array package (dbga2) a 0.81 0.91 1.00 a1 0.15 0.20 0.25 a2 0.40 0.45 0.50 b 0.25 0.30 0.35 1 d 2.35 bsc e 3.73 bsc e 0.75 bsc e1 0.74 ref d 0.75 bsc d1 0.80 ref 1. dimension 'b' is measured at the maximum solder ball diameter. this drawing is for general information only. d a side view top view bottom view 8 solder balls 1 a b c d 2 (e1) e a1 ball pad corner (d1) 1. b a1 a2 d a1 ball pad corner e
21 3368j?seepr?06/07 at25128a_256a 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
22 3368j?seepr?06/07 at25128a_256a 8y7 ? utsap 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. 8y7 , 8-lead (6.00 x 4.90 mm body) ultra-thin soic array package (utsap) y7 b 8y7 10/13/05 common dimensions (unit of measure = mm) symbol min nom max note a ? ? 0.60 a1 0.00 ? 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 3.30 3.40 3.50 e1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 d1 pin 1 id e1 l b e1 e pin 1 index area a e d a1 a
23 3368j?seepr?06/07 at25128a_256a revision history doc. rev. date comments 3368j 6/2007 changed 8y4 to 8y7 package 3368i 3/2007 revision history implemented removed pb product offering
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